In digital applications, it is desirable that a duty cycle of a clock is accurately controlled. A clock with 50% duty cycle has equal portion of high and low waveforms. A high insertion delay in devices results in clock pulse-width degradation. The degradation introduced in the clock by different devices on a SoC is different and hence it is challenging to meet jitter and duty cycle requirements.
Analog and digital duty cycle correction (DCC) circuits are used to maintain the duty cycle of clocks. However, these solutions have shortcomings. The performance of the analog DCC circuits is degraded because of a high start-up time since these are closed loop systems. Also, the analog DCC circuits require high power and also modify both positive and negative edges of the clock for duty cycle correction. Digital DCC circuits are limited by a high lock time since these are closed loop systems. Also, digital DCC circuits modify both positive and negative edges of the clock for duty cycle correction.